The invention relates to a system and process for interfacial adhesion and, more particularly, to a system and process for improved interfacial adhesion of dielectrics using patterned roughing.
Laminate structures are used in a number of applications in the field of electronics. In semiconductor chips, integrated chips and various electric devices, such as capacitors, inductors, and resistors, materials are applied to one another in layers, thereby creating laminate structures. To maintain the integrity of the chips and devices, and ensure their reliability, it is generally necessary for the layers to adhere to each other. However, due to desired electrical properties and capabilities, it may be necessary to create a laminate structure where two adjacent layers are formed of materials that have poor adherence properties relative to each other. This may lead to difficulties in creating a chip or device that has the necessary electrical properties while still maintaining integrity and reliability.
Dielectric materials having a low dielectric constant, based on the composition of the material(s) used, often have poor interface adhesion to other materials used in the same device. This poor interface adhesion can lead to decreased reliability of a device, as materials can separate, slip and/or delaminate, thereby causing faults and failures. Moreover, poor interfacial adhesion may be found in other materials that are adhered in a semiconductor chip level environment.
Various attempts have been made to improve interface adhesion to eliminate the effects of dicing. The dicing process may introduce flaws at the edge of a semiconductor device or chip. Such flaws can actually initiate delaminating at the dielectric/capacitor interface or at other interfaces. Additional stresses during packaging can propagate the delaminating into active areas of the semiconductor chip, thereby causing degradation and failure.
Interlocking structures currently exist, such as metal interconnecting and interlocking structures. Examples of such structures include Intel® “button” connectors. However, such metal interconnecting and interlocking structures require the introduction of a specific metal layer to the semiconductor device. A metal layer may not be desirable, based on the type of chip or device being fabricated, or the properties and electrical capabilities desired in the chip or device. Further, a metal layer may actually prevent the realization of the very properties and electrical capabilities for which the chip or device is being fabricated.